<div dir="ltr"><br><div class="gmail_extra"><br><div class="gmail_quote">On Mon, Aug 10, 2015 at 1:06 PM, Szilárd Páll <span dir="ltr"><<a href="mailto:pall.szilard@gmail.com" target="_blank">pall.szilard@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
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<div><span style="font-size:12.8000001907349px">Hi,</span>
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<div style="font-size:12.8000001907349px">I ran into the issue that I'm not able to use the number of threads I want to on Power8. The high-end chips have 12 cores with 8-way SMT (96 threads) and I wanted to do a multi-threaded scaling test (without DD) on
1-2 sockets. However, it turns out that it is not possible to run on >32 threads with non-multiples on 32. This is a rather inconvenient limitation on any hardware where the hw thread count is not multiple of 32, e.g. on the Powe8 chip I'd like to run k*12,
k={1..8} threads.</div>
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<div style="font-size:12.8000001907349px">AFAIK the same issues will arise on KNC/L too.</div>
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<div style="font-size:12.8000001907349px">Does this limitation originate from the fact that the force reduction is implemented in a simple manner (power of two binary tree reduce?). If that's the case, should we try to extend this?</div></div></div></div></blockquote><div><br></div><div>No you can run with any number of threads. Only the limit has to be multiples of 32. Thus to run with 96 you would set the limit to 128.</div><div><br></div><div>Roland </div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div><div dir="ltr"><div>
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<div style="font-size:12.8000001907349px">Cheers,<br clear="all">
<div>--<br>
Szilárd</div>
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</blockquote></div><br><br clear="all"><div><br></div>-- <br><div class="gmail_signature">ORNL/UT Center for Molecular Biophysics <a href="http://cmb.ornl.gov" target="_blank">cmb.ornl.gov</a><br>865-241-1537, ORNL PO BOX 2008 MS6309</div>
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