<div dir="ltr"><div>Thanks for getting back! Without CAS we won't get very far, I'm afraid. The kernels would need to be rewritten to dump forces to global memory and reduce them later which will likely completely kill performance (and it's a hassle to do).</div><div><br></div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">I can see what I can do, but perhaps StreamComputing guys would be the<br>ones to ask here because it is their code.<br></blockquote><div><br></div><div>I know the code fairly well, but I double-checked to be sure and (unfortunately) image support never got fixed, see:</div><div><a href="http://redmine.gromacs.org/projects/gromacs/repository/revisions/master/entry/src/gromacs/mdlib/nbnxn_ocl/nbnxn_ocl_data_mgmt.cpp#L208" target="_blank">http://redmine.gromacs.org/projects/gromacs/repository/revisions/master/entry/src/gromacs/mdlib/nbnxn_ocl/nbnxn_ocl_data_mgmt.cpp#L208</a><br></div><div><a href="http://redmine.gromacs.org/projects/gromacs/repository/revisions/master/entry/src/gromacs/mdlib/nbnxn_ocl/nbnxn_ocl_data_mgmt.cpp#L423" target="_blank">http://redmine.gromacs.org/projects/gromacs/repository/revisions/master/entry/src/gromacs/mdlib/nbnxn_ocl/nbnxn_ocl_data_mgmt.cpp#L423</a><br></div><div><br></div><div>So image support is definitely not in the way of using radeonsi - and even if we implement it, keeping a version with simple gmem direct acesses for the latter parameter lookup and the analytical estimate iso tabulated Ewald correction (former) will always remain as an option. </div><div><br></div><div>Cheers,</div><div class="gmail_extra"><div><div class="gmail_signature">--<br>Szilárd</div></div>
<br><div class="gmail_quote">On Fri, Nov 27, 2015 at 8:35 PM, Vedran Miletić <span dir="ltr"><<a href="mailto:rivanvx@gmail.com" target="_blank">rivanvx@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">After a bit of compiling of latest llvm/clang/libclc/mesa, on r600g we<br>
get as far as:<br>
<br>
Running on 1 node with total 2 cores, 2 logical cores, 1 compatible GPU<br>
Hardware detected on host akari (the node of MPI rank 0):<br>
CPU info:<br>
Vendor: AuthenticAMD<br>
Brand: AMD Athlon(tm) 64 X2 Dual Core Processor 3600+<br>
SIMD instructions most likely to fit this hardware: SSE2<br>
SIMD instructions selected at GROMACS compile time: SSE2<br>
GPU info:<br>
Number of GPUs detected: 1<br>
#0: name: AMD CAICOS (DRM 2.43.0, LLVM 3.8.0), vendor: AMD, device<br>
version: OpenCL 1.1 MESA 11.1.0-devel, stat: compatible<br>
<br>
Reading file em.tpr, VERSION 5.1-dev-20150219-7c30fcf-unknown (single precision)<br>
Note: file tpx version 100, software tpx version 106<br>
Using 1 MPI process<br>
Using 2 OpenMP threads<br>
<br>
1 compatible GPU is present, with ID 0<br>
1 GPU auto-selected for this run.<br>
Mapping of GPU ID to the 1 PP rank in this node: 0<br>
<br>
Selecting kernel for AMD<br>
LLVM ERROR: Cannot select: 0x1214be0: i32,ch = AtomicCmpSwap<Volatile<br>
LDST4[%1034(addrspace=1)]> 0x1d514f0, 0x152efe0, 0xfd3b00, 0x12170c0<br>
0x152efe0: i32,ch = CopyFromReg 0x1d514f0, Register:i32 %vreg266<br>
0x100a750: i32 = Register %vreg266<br>
0xfd3b00: i32,ch = CopyFromReg 0x1d514f0, Register:i32 %vreg268<br>
0x100b200: i32 = Register %vreg268<br>
0x12170c0: i32 = bitcast 0x12228b0<br>
0x12228b0: f32 = fadd 0x12145f0, 0xfd1fa0<br>
0x12145f0: f32,ch = CopyFromReg 0x1d514f0, Register:f32 %vreg265<br>
0x12164e0: f32 = Register %vreg265<br>
0xfd1fa0: f32 = bitcast 0xfd3b00<br>
0xfd3b00: i32,ch = CopyFromReg 0x1d514f0, Register:i32 %vreg268<br>
0x100b200: i32 = Register %vreg268<br>
In function: nbnxn_kernel_ElecEw_VdwLJ_F_opencl<br>
<br>
Tom Stellard said this is due to missing global atomic compare and<br>
swap on r600, which will be very difficult to implement. So, this is<br>
as far as we get with older cards. I'm going to try radeonsi next<br>
week.<br>
<div class=""><div class="h5"><br>
Regards,<br>
Vedran<br>
<br>
--<br>
Vedran Miletić<br>
<a href="http://vedranmileti.ch/" rel="noreferrer" target="_blank">http://vedranmileti.ch/</a><br>
--<br>
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